fn3104 rev.4.00 page 1 of 10 august 2002 fn3104 rev.4.00 august 2002 AD7520, ad7521 10-bit, 12-bit, multiplying d/a converters datasheet the AD7520 and ad7521 are monolithic, high accuracy, low cost 10-bit and 12-bit resolution, multiplying digital-to-analog converters (dac). intersil?s thin-film on cmos processing gives up to 10-bit accuracy with ttl/cmos compatible operation. digital inputs are fu lly protected aga inst static discharge by diodes to ground and positive supply. typical applications include digital/analog interfacing, multiplication and division, programmable power supplies, crt character generation, digitally controlled gain circuits, integrators and attenuators, etc. features ? AD7520, 10-bit resolution; 8-bit linearity ? ad7521, 12-bit resolution; 10-bit linearity ? low power dissipation (max). . . . . . . . . . . . . . . . . 20mw ? low nonlinearity tempco at 2ppm of fsr/ o c ? current settling time to 0.05% of fsr . . . . . . . . . . 1.0 ? s ? supply voltage range . . . . . . . . . . . . . . . . . ? 5v to +15v ? ttl/cmos compatible ? full input static protection ordering information part number linearity (inl, dnl) temp. range ( o c) package pkg. no. AD7520jn 0.2% (8-bit) 0 to 70 16 ld pdip e16.3 ad7521ln 0.05% (10- bit) 0 to 70 18 ld pdip e18.3 pinouts AD7520 (pdip) top view ad7521 (pdip) top view 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 i out1 i out2 gnd bit 1 (msb) bit 2 bit 3 bit 5 bit 4 r feedback v+ bit 10 (lsb) bit 9 bit 8 bit 7 bit 6 v ref i out1 i out2 gnd bit 1 (msb) bit 2 bit 3 bit 5 bit 4 r feedback v+ bit 11 bit 9 bit 8 bit 7 v ref 10 11 12 13 14 15 16 17 18 9 8 7 6 5 4 3 2 1 bit 12 (lsb) bit 10 bit 6
AD7520, ad7521 fn3104 rev.4.00 page 2 of 10 august 2002 absolute maximum ratings thermal information supply voltage (v+ to gnd) . . . . . . . . . . . . . . . . . . . . . . . . . . .+17v v ref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? 25v digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . v+ to gnd output voltage compliance . . . . . . . . . . . . . . . . . . . . . -100mv to v+ operating conditions temperature ranges jn, ln versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 70 o c thermal resistance (typical, note 1) ? ja ( o c/w) ? jc ( o c/w) 16 ld pdip package 90 n/a 18 ld pdip package 80 n/a maximum junction temperature (plastic packages) . . . . . . .150 o c maximum storage temperature range . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. the digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy elec trostatic fields. keep unused units in conductive foam at all times. do not apply voltages higher than v dd or less than gnd potential on any terminal except v ref and r feedback . 1. ? ja is measured with the component mounted on a low effective ther mal conductivity test board in free air. see tech brief tb379 fo r details. electrical specifications v+ = +15v, v ref = +10v, t a = 25 o c unless otherwise specified parameter test conditions AD7520 ad7521 units min typ max min typ max system performance (note 2) resolution 10 10 10 12 12 12 bits nonlinearity j (note 3) (figure 2) -10v ? v ref ? +10v -- ? 0.2 (8-bit) -- -% of fsr l -10v ? v ref ? +10v (figure 2) -- ? 0.05 (10-bit) -- ? 0.05 (10-bit) % of fsr nonlinearity tempco -10v ? v ref ? +10v (notes 3, 4) -- ? 2- - ? 2 ppm of fsr/ o c gain error - ? 0.3 - - ? 0.3 - % of fsr gain error tempco - - ? 10 - - ? 10 ppm of fsr/ o c output leakage current (either output) over the specified temperature range -- ? 200 - - ? 200 na dynamic characteristics output current settling time to 0.05% of fsr (all digital inputs low to high and high to low) (note 4) (figure 7) -1.0 - -1.0 - ? s feedthrough error v ref = 20v p-p , 100khz all digital inputs low (note 4) (figure 6) - - 10 - - 10 mv p-p reference input input resistance all digital inputs high i out1 at ground 5 10 20 5 10 20 k ? analog output output capacitance i out1 all digital inputs high (note 4) (figure 5) - 200 - - 200 - pf i out2 -75--75-pf i out1 all digital inputs low (note 4) (figure 5) -75--75-pf i out2 - 200 - - 200 - pf output noise both outputs (note 4) (figure 4) - equivalent to 10k ? - - equivalent to 10k ? - johnson noise digital inputs low state threshold, v il over the specified temperature range v in = 0v or +15v -- 0.8-- 0.8v high state threshold, v ih 2.4 - - 2.4 - - v input current, i il , i ih -- ? 1- - ? 1 ? a input coding see tables 1 and 2 binary/offset binary
AD7520, ad7521 fn3104 rev.4.00 page 3 of 10 august 2002 functional diagram power supply characteristics power supply rejection v+ = 14.5v to 15.5v (note 3) (figure 3) - ? 0.005 - - ? 0.005 - % fsr/% ? v+ power supply voltage range +5 to +15 +5 to +15 v i+ all digital inputs at 0v or v+ excluding ladder network - ? 1-- ? 1- ? a all digital inputs high or low excluding ladder network -- 2-- 2ma total power dissipation including the ladder network - 20 - - 20 - mw notes: 2. full scale range (fsr) is 10v for unipolar and ? 10v for bipolar modes. 3. using internal feedback resistor r feedback . 4. guaranteed by design, or charac terization and not production tested. 5. accuracy not guaranteed unless outputs at gnd potential. 6. accuracy is tested and guaranteed at v+ = 15v only. electrical specifications v+ = +15v, v ref = +10v, t a = 25 o c unless otherwise specified (continued) parameter test conditions AD7520 ad7521 units min typ max min typ max pin descriptions AD7520 ad7521 pin name description 11i out1 current out summing junction of the r2r ladder network. 22i out2 current out virtual ground, return path for the r2r ladder network. 3 3 gnd digital ground. ground potential for digital side of d/a. 4 4 bits 1(msb) most significant digital data bit. 5 5 bit 2 digital bit 2. 6 6 bit 3 digital bit 3. 7 7 bit 4 digital bit 4. 8 8 bit 5 digital bit 5. 9 9 bit 6 digital bit 6. 10 10 bit 7 digital bit 7. 11 11 bit 8 digital bit 8. 12 12 bit 9 digital bit 9. 13 13 bit 10 digital bit 10 (ad7521). least significant digital data bit (AD7520). - 14 bit 11 digital bit 11 (ad7521). - 15 bit 12 least significant digital data bit (ad7521). 14 16 v+ power supply +5v to +15v. 15 17 v ref voltage reference input to set the outpu t range. supplies the r2r resistor ladder. 16 18 r feedback feedback resistor used for the current to vo ltage conversion when using an external op amp. 20k ? gnd i out2 i out1 r feedback bit 3 bit 2 msb v ref 20k ? 20k ? 20k ? 20k ? 20k ? 10k ? 10k ? 10k ? 10k ? spdt nmos switches 10k ? notes: switches shown for digital inputs ?high?. resistor values are typical.
AD7520, ad7521 fn3104 rev.4.00 page 4 of 10 august 2002 definition of terms nonlinearity: error contributed by deviation of the dac transfer function from a ?best st raight line? through the actual plot of transfer function. no rmally expressed as a percentage of full scale range or in (sub)multiples of 1 lsb. resolution: it is addressing the smallest distinct analog output change that a d/a converter can produce. it is commonly expressed as the number of c onverter bits. a converter with resolution of n bits can resolve output changes of 2 -n of the full- scale range, e.g., 2 -n v ref for a unipolar conversion. resolution by no means implies linearity. settling time: time required for the output of a dac to settle to within specified error band around its final value (e.g., 1 / 2 lsb) for a given digital input change, i.e., all digital inputs low to high and high to low. gain error: the difference between actual and ideal analog output values at full scale range, i.e., all digital inputs at high state. it is expressed as a perc entage of full scale range or in (sub)multiples of 1 lsb. feedthrough error: error caused by capacitive coupling from v ref to i out1 with all digital inputs low. output capacitance: capacitance from i out1 and i out2 terminals to ground. output leakage current: current which appears on i out1 terminal when all digital inputs are low or on i out2 terminal when all digital inputs are high. detailed description the AD7520 and ad7521 are monolithic, multiplying d/a converters. a highly stable thin film r-2r resistor ladder network and nmos spdt switch es form the basis of the converter circuit, cmos level shifters permit low power ttl/cmos compatible operation. an external voltage or current reference and an operationa l amplifier are all that is required for most voltage output applications. a simplified equivalent circuit of the dac is shown in the functional diagram . the nmos spdt switches steer the ladder leg currents between i out1 and i out2 buses which must be held either at ground potential. this configuration maintains a constant current in each ladder leg independent of the input code. converter errors are further reduced by using separate metal interconnections between the major bits and the outputs. use of high threshold switches reduce offset (leakage) errors to a negligible level. the level shifter circuits are comprised of three inverters with positive feedback from the output of the second to the first, see figure 1. this configuration re sults in ttl/cmos compatible operation over the full military te mperature range. with the ladder spdt switches driven by the level shifter, each switch is binarily weighted for an on resistance proportional to the respective ladder leg current. this assures a constant voltage drop across each switch, creating equipotentia l terminations for the 2r ladder resistors and highly accurate leg currents. v+ dtl/ttl/ cmos input 13 4 5 6 7 2 89 to ladder i out2 i out1 figure 1. cmos level shifter and switch test circuits the following test circuits apply for the ad 7520. similar circuits are used for the ad7521. figure 2. nonlinearity figure 3. power supply rejection 10-bit binary counter gnd 15 16 1 5 4 13 32 AD7520 bit 1 (msb) bit 10 (lsb) linearity error x 100 r feedback i out1 i out2 ha2600 - + v ref bit 1 (msb) bit 10 bit 11 bit 12 10k ? 0.01% 1m ? 10k ? 0.01% clock +15v v ref ha2600 - + 12-bit reference dac 15 16 1 5 4 13 32 AD7520 bit 1 (msb) bit 10 (lsb) ha2600 - + ha2600 - + 500k ? ungrounded sine wave generator 40hz 1v p-p 5k ? 0.01% 5k 0.01% r feedback +15v +10v v ref i out1 i out2 14 gnd v error x 100
AD7520, ad7521 fn3104 rev.4.00 page 5 of 10 august 2002 applications unipolar binary operation the circuit configuration for op erating the AD7520 in unipolar mode is shown in figure 8. similar circuits can be used for ad7521. with positive and negative v ref values the circuit is capable of 2-quadrant multiplication. the digital input code/analog output value table for unipolar mode is given in table 1. zero offset adjustment 1. connect all digital inputs to gnd. 2. adjust the offset ze ro adjust trimpot of the output operational amplifier for 0v at v out . gain adjustment 1. connect all digital inputs to v+. 2. monitor v out for a -v ref (1-2 -n ) reading. (n = 8 for AD7520 and n = 10 for ad7521). figure 4. noise figure 5. output capacitance figure 6. feedthrough error figure 7. output current settling time test circuits the following test circuits apply for the ad 7520. similar circuits are used for the ad7521. (continued) 15 2 5 4 13 3 1 AD7520 101aln - + 0.1 ? f i out1 i out2 14 10k ? v out 100 ? 15 ? f 1k +15v 50k ? 1k ? -50v f = 1khz bw = 1hz quan tech model 134d wave analyzer +11v (adjust for v out = 0v) 15 16 1 5 4 13 3 2 AD7520 bit 1 (msb) bit 10 (lsb) 14 +15v nc scope 100mv p-p 1mhz nc 1k ? +15v 15 16 1 5 4 13 3 2 AD7520 bit 1 (msb) bit 10 (lsb) 14 +15v v ref = 20v p-p gnd i out1 i out2 2 3 6 v out 100khz sine wave ha2600 - + 15 1 5 4 13 3 2 AD7520 bit 1 (msb) bit 10 (lsb) 14 +15v scope +100mv 100 ? gnd v ref digital i out2 extrapolate 5t: 1% settling (1mv) 8t: 0.03% settling t = rise time input +5v 0v +10v 15 16 1 5 4 13 3 2 AD7520 bit 1 (msb) bit 10 (lsb) 14 +15v v ref gnd i out1 i out2 6 v out - + r feedback digital input figure 8. unipolar binary operation (2-quadrant multiplication) table 1. code table - unlpolar binary operation digital input analog output 1111111111 -v ref (1-2 -n ) 1000000001 -v ref ( 1 / 2 + 2 -n ) 1000000000 -v ref /2 0111111111 -v ref ( 1 / 2 -2 -n ) 0000000001 -v ref (2 -n ) 0000000000 0 notes: 1. lsb = 2 -n v ref . 2. n = 8 for 7520 n = 10 for 7521.
AD7520, ad7521 fn3104 rev.4.00 page 6 of 10 august 2002 3. to decrease v out , connect a series resistor (0 to 250 ? ) between the reference voltage and the v ref terminal. 4. to increase v out , connect a series resistor (0 to 250 ? ) in the i out1 amplifier feedback loop. bipolar (offset binary) operation the circuit configuration for operating the AD7520 in the bipolar mode is given in figure 9. similar circuits can be used for ad7521. using offset binary digital input codes and positive and negative referenc e voltage values, 4-quadrant multiplication can be realized. the ?digital input code/analog output value? table for bipolar mode is given in table 2. a ?logic 1? input at any digital input forces the corresponding ladder switch to steer the bit current to iout1 bus. a ?logic 0? input forces the bit current to iout2 bus. for any code the iout1 and iout2 bus currents are complements of one another. the current amplifier at iout2 changes the polarity of iout2 current and the transconductance amplifier at iout1 output sums the two currents. th is configuration doubles the output range. the difference current resulting at zero offset binary code, (msb = ?logic 1?, all other bits = ?logic 0?), is corrected by using an external resistor, (10mw), from vref to iout2 . offset adjustment 1. adjust v ref to approximately +10v. 2. connect all digital inputs to ?logic 1?. 3. adjust i out2 amplifier offset adjust trimpot for 0v ? 1mv at i out2 amplifier output. 4. connect msb (bit 1) to ?logic 1? and all other bits to ?logic 0?. 5. adjust i out1 amplifier offset adjust trimpot for 0v ? 1mv at v out . gain adjustment 1. connect all digital inputs to v+. 2. monitor v out for a -v ref (1-2 -(n-1) volts reading. (n = 8 for AD7520, and n = 10 for ad7521.). 3. to increase v out , connect a series resistor of up to 250 ? between v out and r feedback . 4. to decrease v out , connect a series resister of up to 250 ? between the reference voltage and the v ref terminal. table 2. blpolar (offset binary) code table digital input analog output 1111111111 -v ref (1-2 -(n-1) ) 1000000001 -v ref (2 -(n-1) ) 1000000000 0 0111111111 v ref (2 -(n-1) ) 0000000001 v ref (1-2 -(n-1) ) 0000000000 v ref notes: 1. lsb = 2 -(n-1) v ref . 2. n = 8 for 7520 n = 10 for 7521. 15 16 1 5 4 13 3 2 AD7520 bit 1 bit 10 14 +15v v ref i out2 6 v out - + r feedback 6 - + (msb) (lsb) i out1 r1 10k 0.01% r2 10k 0.01% digital input r3 10m ? figure 9. bipolar operation (4-quadrant multiplication)
AD7520, ad7521 fn3104 rev.4.00 page 7 of 10 august 2002 die characteristics die dimensions: 101 mils x 103 mils (2565 ? m x 2616 ? m) metallization: type: pure aluminum thickness: 10 ?? 1k ? passivation: type: psg/nitride psg: 7 ?? 1.4k ? nitride: 8 ?? 1.2k ? process: cmos metal gate metallization mask layout AD7520 pin 3 gnd pin 2 i out 2 pin 1 i out 1 pin 16 r feedback pin 15 v ref pin 14 v+ nc nc pin 12 pin 4 bit 1 (msb) pin 5 bit 2 pin 6 bit 3 pin 7 bit 4 pin 11 bit 8 pin 10 bit 7 pin 9 bit 6 pin 8 bit 5 bit 9 pin 13 bit 10 (lsb)
AD7520, ad7521 fn3104 rev.4.00 page 8 of 10 august 2002 die characteristics die dimensions: 101 mils x 103 mils (2565 ? m x 2616 ? m) metallization: type: pure aluminum thickness: 10 ?? 1k ? passivation: type: psg/nitride psg: 7 ?? 1.4k ? nitride: 8 ?? 1.2k ? process: cmos metal gate metallization mask layout ad7521 pin 3 gnd pin 2 i out 2 pin 1 i out 1 pin 18 r feedback pin 17 v ref pin 16 v+ pin 12 pin 4 bit 1 (msb) pin 5 bit 2 pin 6 bit 3 pin 7 bit 4 pin 11 bit 8 pin 10 bit 7 pin 9 bit 6 pin 8 bit 5 bit 9 pin 13 bit 10 pin 14 bit 11 pin 15 bit 12 (lsb)
AD7520, ad7521 fn3104 rev.4.00 page 9 of 10 august 2002 dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the in ch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in je- dec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shal l not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendic- ular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e16.3 (jedec ms-001-bb issue d) 16 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8, 10 c 0.008 0.014 0.204 0.355 - d 0.735 0.775 18.66 19.68 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n16 169 rev. 0 12/93
fn3104 rev.4.00 page 10 of 10 august 2002 AD7520, ad7521 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2002. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the in ch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are m easured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shal l not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendic- ular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e18.3 (jedec ms-001-bc issue d) 18 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8, 10 c 0.008 0.014 0.204 0.355 - d 0.845 0.880 21.47 22.35 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n18 189 rev. 0 12/93
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